As technology advances, memories in semiconductor devices have become larger and more advanced. While such large, compact memories provide the functionality required for current data processing systems, these memories have also stretched manufacturing and design technology limits. For example, as memories have become more dense, the memory cells themselves have become considerably smaller. As dimensions decrease, the difficulties associated with manufacturing functioning devices increases. Furthermore, as memories become larger, more cells are disbursed along conductors within the memory, thus increasing capacitive loading in a manner that adversely affects the functionality of the device. To understand the issues associated with larger memories, a description of a typical semiconductor memory will be provided below.
A semiconductor memory typically includes a memory cell array that has a grid of bitlines and wordlines, with memory cells disposed at intersections of the bitlines and wordlines. During operation, the bitlines and wordlines are selectively asserted or negated to enable at least one of the memory cells to be read or written. Furthermore, one type of semiconductor memory cell array is a differential signal memory array. In traditional differential signal memory arrays, a 6-device memory cell is utilized. In the 6-device memory cell, four transistors are configured to form a cross-coupled latch or a memory cell for storing data. The remaining two transistors are used to obtain access to the memory cell. During a "read" access, differential data stored within the memory cell is transferred to an attached bitline pair. Differential voltage is allowed to develop on the bitlines until there is sufficient offset between bitlines to reliably sense the binary state of the memory cell. Such an offset is typically in the range of 100-200 millivolts. With the completion of the read access, the differential bitline pairs are clamped together and restored to a "high" logic level voltage to cancel an offset generated during the read operation.
Conversely, during a "write" access, data is written into the memory cell through the differential bitline pair. In general, one side of the bitline pair is driven to a logic low level potential and a remaining side of the differential pair is driven to a high voltage level less a threshold voltage of the transistor. Following the write access, the differential bitline pair is typically restored to a high logic level voltage prior to a next read or write access to the memory cell. For a traditional memory array, the time required for a sufficient bitline offset development to reliably read the memory cell, in addition to the time required to restore one-half of the differential bitline pair ground potential to the logic high voltage after a write operation, defines a minimum cycle time for the array.
Improvements to either a bitline offset development rate, or a bitline restore time following a write access, increase performance of the memory structure as a whole. However, in a large memory array which typically includes an array organized in long column bitlines, together with many rows, the length of an array bitline limits the improvements that may be accomplished.
Thus, increasing demands for larger memories have driven increases in bitline length and loading as memory designers place additional cells along a bitline within a memory array to implement denser memory arrays. The additional length of the bitline (referred to as wire length) and device count per bitline add wire and diffusion capacitance to an already highly capacitive environment. As previously set forth, additional time is then required to charge and discharge this extra capacitance. Such additional time equates to increased read and write access times and increased cycle times, and, therefore, to slower performance.
Therefore, a need exists for a semiconductor memory that allows additional cells to be placed along a bitline in a memory array, while preserving performance of the memory system.